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PIC16F87X

DS30292C-page 78

2001 Microchip Technology Inc.

9.2.5

MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET, or when the MSSP module is

disabled. Control of the I2C bus may be taken when the

P bit is set, or the bus is idle, with both the S and P bits

clear.

In Master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (an SSP interrupt will occur if

enabled):

START condition

STOP condition

Data transfer byte transmitted/received

Acknowledge transmit

Repeated START

FIGURE 9-9:

SSP BLOCK DIAGRAM (I

2C MASTER MODE)

9.2.6

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a RESET or

when the MSSP module is disabled. Control of the I2C

bus may be taken when bit P (SSPSTAT<4>) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the STOP condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored for arbitration to see if the signal level is the

expected output level. This check is performed in hard-

ware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

Address Transfer

Data Transfer

A START Condition

A Repeated START Condition

An Acknowledge Condition

Read

Write

SSPSR

START bit, STOP bit,

SSPBUF

Internal

Data Bus

Set/Reset, S, P, WCOL (SSPSTAT)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

SCL

SCL in

Bus Collision

SDA in

Rec

ive

nable

Cloc

Cntl

loc

Arbit

rat

Det

(hold

loc

source

)

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0,

START bit Detect,

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

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